Production method for semiconductor substrate and semiconductor element

ABSTRACT

A reaction prevention layer is formed to prevent Si from reacting with a gallium nitride group semiconductor (semiconductor crystal A) which is deposited after the reaction prevention layer is formed. By forming a reaction prevention layer comprising a material whose melting point or thermal stability is higher than that of a gallium nitride group semiconductor, e.g., AlN, on a sacrifice layer, a reaction part is not formed in the semiconductor substrate deposited on the reaction prevention layer when the gallium nitride group semiconductor is grown by crystal growth for a long time. In short, owing to the effect that the reaction prevention layer prevents silicon (Si) from diffusing, the reaction part is generated only in the sacrifice layer and it is never formed at the upper portion of the reaction prevention layer even by growing the semiconductor crystal A at a high temperature for a long time.

TECHNICAL FIELD

The present invention relates to a method for producing a semiconductorsubstrate by growing a crystal of group III nitride compoundsemiconductor on a base substrate comprising silicon (Si). The presentinvention also relates to a semiconductor device, e.g., a group IIInitride compound semiconductor device, formed on such a semiconductorsubstrate obtained by above method.

BACKGROUND ART

FIG. 5 is a schematic cross-sectional view showing a conventionalsemiconductor crystal formed on a Si substrate (a base substrate) bycrystal growth. MOCVD is applied in a process of crystal growth of thesemiconductor crystal. As shown in FIG. 5, a semiconductor crystal (e.g.GaN crystal) grown at a high temperature on a Si substrate (basesubstrate) by using a conventional technique has a reaction part,dislocations and cracks.

Dislocations and cracks are occurred because of stress which isgenerated owing to difference of thermal expansion coefficients anddifference of lattice constants between different kinds of materials. Sowhen such a crystal growth substrate is used for fabricating each kindof semiconductor devices, the characteristics of the device isdeteriorated.

When the base substrate consisting of silicon (Si) except for the grownlayer is removed so as to obtain a free-standing substrate (crystal),the substrate cannot have larger area (1 cm² and bigger) because ofdislocations and cracks described above.

At the temperature for crystal growth of an objective semiconductorsubstrate (semiconductor crystal A), or around 1000° C. to 1150° C.,silicon (Si) and gallium nitride (GaN) happen to react (“reaction part”in FIG. 5). As a result, it is not easy to obtain a single crystallineGaN substrate by applying a crystal growing process in a hightemperature.

A method of using a silicon thin film, which hardly generates stressdescribed above, alone as a crystal growth substrate in order to obtainmonocrystalline GaN substrate is reported. But such a thin film iseasily destroyed and it is not easy to handle the thin film directlybefore carrying out crystal growth. Accordingly, it was difficult tomanufacture semiconductor substrates each having a larger area and toobtain a higher yield rate of the semiconductor substrates by employingsuch conventional methods.

DISCLOSURE OF THE INVENTION

The present invention has been accomplished in order to overcome theaforementioned drawbacks. An object of the present invention is toeffectively produce a semiconductor crystal of high quality having nocrack or polycrystalline lump (reaction part which reacts at a hightemperature) by using silicon (Si) which can be provided atcomparatively low cost as a base substrate. Other object of the presentinvention is to produce semiconductor devices of high quality which areformed by using a high-quality semiconductor crystal as a crystal growthsubstrate.

The following means may be useful to overcome the above-describeddrawbacks.

That is, the first aspect of the present invention provides a method forproducing a semiconductor substrate in which a semiconductor crystal Acomprising a Group III nitride compound semiconductor is grown on a basesubstrate comprising silicon (Si), comprising the steps of: a sacrificelayer forming process in which a sacrifice layer comprisingapproximately the same kind of semiconductor as the semiconductorcrystal A is formed on the base substrate by crystal growth; a reactionprevention layer forming process in which a reaction prevention layermade of a monocrystalline material B whose melting point or thermalstability is higher than that of the semiconductor crystal A andpreventing silicon (Si) from diffusing is deposited on the sacrificelayer; and a crystal growth process for growing a semiconductorsubstrate made of the semiconductor crystal A on the reaction preventionlayer by crystal growth.

Here, the semiconductor substrate comprising the semiconductor crystal Amay have a single layer structure. Alternatively, it may also have amultiple layer structure.

As used herein, the term group III nitride compound semiconductorgenerally refers to a binary, ternary, or quaternary semiconductorhaving arbitrary compound crystal proportions and represented byAl_(x)Ga_(y)In_((1-x-y))N (0≦x≦1, 0≦y≦1, 0≦x+y≦1). A semiconductor dopedwith p-type or n-type impurity is also included in a group III nitridecompound semiconductor described in the present specification.

Group III elements (Al, Ga, In) may be partially replaced with boron (B)or thallium (Tl), and nitrogen (N) atoms may be completely or partiallyreplaced with phosphorus (P), arsenic (As), antimony (Sb), or bismuth(Bi). Such a semiconductor may also be included in “a group III nitridecompound semiconductor” in the present specification.

Examples of the aforementioned p-type impurity include magnesium (Mg)and calcium (Ca).

Examples of the aforementioned n-type impurity include silicon (Si),sulfur (S), selenium (Se), tellurium (Te), and germanium (Ge).

These impurities may be incorporated in combination of two or morespecies, and a p-type impurity and an n-type impurity may beincorporated in combination.

FIG. 1 illustrates a schematic cross-sectional view which explains abasic idea of a method for producing a semiconductor crystal in thepresent invention. A reaction prevention layer is formed to prevent Sifrom reacting with a gallium nitride group semiconductor (semiconductorcrystal A) which is deposited after the reaction prevention layer isformed. By forming a reaction prevention layer (monocrystalline materialB) comprising a material whose melting point or thermal stability ishigher than that of a gallium nitride group semiconductor, e.g., SiC andAlN, on the sacrifice layer, a reaction part described above is notformed in the semiconductor substrate (semiconductor crystal A)deposited on the reaction prevention layer when the gallium nitridegroup semiconductor (semiconductor crystal A) is grown by crystal growthfor a long time.

In short, owing to the effect that the reaction prevention layerprevents silicon (Si) from diffusing, the reaction part is generatedonly in the sacrifice layer and it is never formed at the upper portionof the reaction prevention layer even by growing the semiconductorcrystal A at a high temperature for a long time.

By generating the reaction part in the sacrifice layer intentionally, asemiconductor layer comprising a polycrystalline GaN (high temperaturereaction part made of polycrystalline lump) is formed between thesilicon (Si substrate) and the reaction prevention layer. As a result,after the reaction part is formed, stress which acts to the reactionprevention layer is relaxed and hardly functions so as to form a crackon the reaction prevention layer. As a result, cracks which penetratethe reaction prevention layer in longitudinal direction are hardlygenerated. And because the base substrate (Si substrate) and the galliumnitride group semiconductor (semiconductor crystal A) can be completelyinterrupted by the reaction prevention layer having no cracks whichpenetrate in longitudinal direction, generation of the above-describedreaction part in the semiconductor substrate (semiconductor crystal A)can be prevented more securely.

Owing to the polycrystalline lump, stress caused between the basesubstrate and the semiconductor substrate is relaxed. That enables todecrease unnecessary stress which acts to a growing semiconductorsubstrate when the semiconductor substrate (objective semiconductorcrystal A) is grown by crystal growth, to thereby reduce generation ofdislocations and cracks.

Owing to the stress relaxing action described above, dislocations hardlyoccurs in the gallium nitride group semiconductor (semiconductor crystalA), and generation of cracks can be remarkably reduced.

Further, because the reaction part described above is made ofpolycrystalline lump of GaN, the reaction part is structurally weak andfragile, and has a small endurance toward external force and innerstress. Accordingly, an objective semiconductor substrate can be easilyseparated from the base substrate (Si substrate) at the sacrifice layercomprising the reaction part.

According to those actions and their synergism, it becomes possible oreasier to obtain a semiconductor substrate (semiconductor crystal A) ofhigh quality whose dislocation concentration is sufficiently controlledand which does not have reaction part and cracks.

The second aspect is drawn to a method of the first aspect, wherein thesemiconductor crystal A comprises a group III nitride compoundsemiconductor having a composition of Al_(x)Ga_(y)In_((1-x-y))N(0≦x<0.9, 0.1<y≦1, 0<x+y≦1).

The third aspect is drawn to a method of the first or second aspect,wherein at least one of silicon carbide (SiC), aluminum nitride (AlN),and spinel (MgAl₂O₄) is used as monocrystalline material B forming thereaction prevention layer.

The fourth aspect is drawn to a method of the first or second aspect,wherein AlGaN, AlInN, or AlGaInN, in which aluminum composition ratio isat least 0.30 or more, is used as monocrystalline material B forming thereaction prevention layer.

Further, a material having comparatively strong interatomic bindingenergy, high thermal stability (fusing point) and high stability may bepreferably employed as monocrystalline material B.

The fifth aspect is drawn to a method according to any one of the firstto fourth aspects, wherein thickness of the reaction prevention layer isin a range of 0.1 μm to 2 μm. More preferably, thickness of the reactionprevention layer is in a range of 0.5 μm to 1.5 μm.

When the thickness of each reaction prevention layer is too small,because the thickness is not uniform and the monocrystalline material Bis not a material with sufficient stability, gallium (Ga) or galliumnitride (GaN) and silicon (Si) cannot be completely interrupted. As aresult, formation of reaction part (poly-crystalline GaN) may not beprevented sufficiently.

When the thickness of each reaction prevention layer is too large,cracks tends to be generated in the reaction prevention layer, andgallium (Ga) or gallium nitride (GaN) and silicon (Si) in thesemiconductor crystal A (semiconductor substrate) formed thereon cannotbe completely interrupted. As a result, formation of reaction part maynot be prevented sufficiently, to thereby generate the reaction part inthe semiconductor substrate (the upper layer semiconductor crystal A).

When the thickness of each reaction prevention layer is too large, moretime and materials are needed to deposit the reaction prevention layer,to thereby unfavorably increase the production cost of the device.

The sixth aspect is drawn to a method according to any one of the firstto fifth aspects, wherein two or more reaction prevention layers aredeposited. By depositing plural numbers of reaction prevention layers,diffusing of silicon can be prevented more securely. As a result,generation of reaction part can be prevented more securely.

The seventh aspect is drawn to a method according to any one of thefirst to sixth aspects, wherein a buffer layer C made of Al_(x)Ga_(1-x)N(0<x≦1) is formed directly on the base substrate or the reactionprevention layer.

Here the buffer layer C is a semiconductor layer made of AlN or AlGaNwhich grows at the temperature around 1100° C. Alternatively, aside fromthe buffer layer C, a middle layer (it may be called just “a bufferlayer” hereinafter) having almost the same compositions as those of thebuffer layer C (e.g., AlN and AlGaN) may be further formed in thesemiconductor substrate (semiconductor crystal A) periodically,alternatively with other layers, or deposited so that the middle layerhas a multiple layer structure.

By depositing such a buffer layer (or a middle layer), stress caused bydifference of lattice constants and acting to the semiconductor crystalA may be relaxed by the same action principle as that of theconventional one. As a result, crystallinity of the device is improved.

Such action and effect may be seen remarkable especially when themonocrystalline material B constructing the reaction prevention layer issuch as silicon carbide (SiC). In short, it is more preferable at thistime to form the buffer layer C on the reaction prevention layer.

The eighth aspect is drawn to a method according to the seventh aspect,wherein two or more buffer layers C are laminated. For example, twobuffer layers C are formed in total on each upper surface of the basesubstrate (Si substrate) and the reaction prevention layer. By employingmultiple layer structure of the buffer layers, action and effect as inthe seventh aspect can be obtained more securely.

The ninth aspect is drawn to a method according to the seventh or eighthaspect, wherein the buffer layer C is formed to have thickness of 0.01μm to 1 μm. More preferably, thickness of the buffer layer C is in arange of 0.02 μm to 0.5 μm.

When thickness of the buffer layer C is too large, cracks tend to begenerated in the buffer layer and more production time and materials areneeded. That is not favorable to the production cost of the device. Whenthe buffer layer C is too thin, it becomes difficult to form the bufferlayer to have almost uniform thickness. As a result, the buffer layerbecomes to have ununiform thickness (or a portion where it is not grownadequately), crystallinity of the buffer layer tends to be ununiform,and that is not desirable.

The tenth aspect is drawn to a crystal growing process according to anyone of the first to ninth aspects, wherein the semiconductor crystal Ais deposited to have a thickness of 50 μm or more.

The larger thickness of the semiconductor crystal A is, the more tensilestress to the semiconductor substrate (semiconductor crystal A) isrelaxed. That decreases generation of dislocations and cracks in thesemiconductor substrate and at the same time strengthen thesemiconductor substrate. As a result, it becomes easier to handle it asa semiconductor substrate.

The eleventh aspect is drawn to a group III nitride compoundsemiconductor device comprising the semiconductor crystal which isformed by the method of any one of the first to tenth aspects as acrystal growth substrate.

Accordingly, a group III nitride compound semiconductor device, e.g., alight-emiting device such as an LED or a transistor circuit such as anFET, made of a semiconductor which has excellent crystallinity and lessinner stress can be obtained or easily produced.

The twelfth aspect is to form a group III nitride compound semiconductordevice by employing crystal growth in which a semiconductor crystalmanufactured by the method of any one of the first to tenth aspectsfunctions as a crystal growth substrate.

As a result, a group III nitride compound semiconductor device made of asemiconductor which has excellent crystallinity and less inner stresscan be obtained or easily manufactured.

Through employment of the aforementioned aspects of the presentinvention, the aforementioned drawbacks can be overcome effectively andrationally.

That is, the thirteenth aspect of the present invention provides amethod for producing a semiconductor substrate in which a semiconductorcrystal A comprising a Group III nitride compound semiconductor is grownon a base substrate comprising silicon (Si), comprising the steps of: athin film part forming process in which a thin film part comprisingsilicon (Si) is formed as a crystal growth front of the base substrateby forming a cavity right under the crystal growth front of the basesubstrate; a reaction prevention layer forming process in which areaction prevention layer made of a monocrystalline material B whosemelting point or thermal stability is higher than that of thesemiconductor crystal A is deposited on the thin film part; and acrystal growing process for growing the semiconductor crystal A on thereaction prevention layer by crystal growth.

Here, the semiconductor substrate comprising the semiconductor crystal Amay have a single layer structure. Alternatively, it may also have amultiple layer structure.

As used herein, the term group III nitride compound semiconductorgenerally refers to a binary, ternary, or quaternary semiconductorhaving arbitrary compound crystal proportions and represented byAl_(x)Ga_(y)In_((1-x-y))N (0≦x≦1, 0≦y≦1, 0≦x+y≦1). A semiconductor dopedwith p-type or n-type impurity is also included in a group III nitridecompound semiconductor described in the present specification.

Group III elements (Al, Ga, In) may be partially replaced with boron (B)or thallium (Tl), and nitrogen (N) atoms may be completely or partiallyreplaced with phosphorus (P), arsenic (As), antimony (Sb), or bismuth(Bi). Such a semiconductor may also be included in “a group III nitridecompound semiconductor” in the present specification.

Examples of the aforementioned p-type impurity include magnesium (Mg)and calcium (Ca).

Examples of the aforementioned n-type impurity include silicon (Si),sulfur (S), selenium (Se), tellurium (Te), and germanium (Ge).

These impurities may be incorporated in combination of two or morespecies, and a p-type impurity and an n-type impurity may beincorporated in combination.

FIG. 2 illustrates a schematic cross-sectional view which explains abasic idea of a method for producing a semiconductor crystal in thepresent invention. A reaction prevention layer is formed to prevent Sifrom reacting with a gallium nitride group semiconductor (semiconductorcrystal A). By forming a reaction prevention layer (monocrystallinematerial B) comprising a material whose melting point or thermalstability is higher than that of a gallium nitride group semiconductor(semiconductor crystal A), e.g., SiC and AlN, on a base substrate (Sisubstrate), a reaction part described above is not formed around siliconinterface when the gallium nitride group semiconductor (semiconductorcrystal A) is grown by crystal growth for a long time.

By forming a cavity, a thin film is formed at the side of the crystalgrowth front of the silicon (Si substrate), stress which acts to thereaction prevention layer is relaxed, and hardly functions so as to forma crack on the reaction prevention layer in longitudinal direction. As aresult, cracks which penetrate the reaction prevention layer inlongitudinal direction are hardly generated. And because the basesubstrate (Si substrate) and the gallium nitride group semiconductor(semiconductor crystal A) can be completely interrupted by the reactionprevention layer having no cracks which penetrate in longitudinaldirection, generation of the above-described reaction part can beprevented more securely.

Owing to the thin film part and the cavity, stress caused by thedifference of lattice constants of the base substrate and thesemiconductor substrate is relaxed. That enables to decrease unnecessarystress which acts to a growing semiconductor substrate when thesemiconductor substrate (objective semiconductor crystal A) grows bycrystal growth, to thereby reduce generation of dislocations and cracks.

Owing to the stress relaxing action described above, dislocations hardlyoccurs in the gallium nitride group semiconductor (semiconductor crystalA), and generation of cracks can be remarkably reduced.

According to those actions and their synergism, it becomes possible oreasier to obtain a semiconductor substrate (semiconductor crystal A) ofhigh quality whose dislocation concentration is sufficiently suppressedand which does not have reaction part and cracks.

The fourteenth aspect is drawn to a method of the thirteenth aspect,wherein the semiconductor crystal A comprises a group III nitridecompound semiconductor having a composition of Al_(x)Ga_(y)In_((1-x-y))N(0≦x<1, 0<y≦1, 0<x+y≦1).

The fifteenth aspect is drawn to a method of the thirteenth orfourteenth aspect, wherein at least one of silicon carbide (SiC),aluminum nitride (AlN), and spinel (MgAl₂O₄) is used as monocrystallinematerial B forming the reaction prevention layer.

The sixteenth aspect is drawn to a method of the thirteenth orfourteenth aspect, wherein AlGaN, AlInN, or AlGaInN, in which aluminumcomposition ratio is at least 0.30 or more, is used as monocrystallinematerial B forming the reaction prevention layer.

Further, a material having comparatively strong interatomic bindingenergy, high thermal stability (fusing point) and high stability may bepreferably employed as monocrystalline material B.

The seventeenth aspect is drawn to a method according to any one of thethirteenth to sixteenth aspects, wherein thickness of the reactionprevention layer is in a range of 0.1 μm to 2 μm.

When the thickness of each reaction prevention layer is too small,because the thickness is not uniform and the monocrystalline material Bis not a material with sufficient stability, gallium (Ga) or galliumnitride (GaN) and silicon (Si) cannot be completely interrupted. As aresult, formation of reaction part (poly-crystalline GaN) may not beprevented sufficiently.

When thickness of each reaction prevention layer is too large, crackstends to be generated in the reaction prevention layer, and gallium (Ga)or gallium nitride (GaN) and silicon (Si) cannot be completelyinterrupted. As a result, formation of reaction part may not beprevented sufficiently.

When the thickness of each reaction prevention layer is too large, moretime and materials are needed to deposit the reaction prevention layer,to thereby unfavorably increase the production cost of the device.

The eighteenth aspect is drawn to a reaction prevention layer formingprocess according to any one of the thirteenth to seventeenth aspects,wherein a buffer layer C made of Al_(x)Ga_(1-x)N (0<x≦1) is formed onthe reaction prevention layer after said reaction prevention layerforming process.

Here the buffer layer C is a semiconductor layer made of AlN or AlGaNwhich grows at the temperature around 1100° C. Alternatively, aside fromthe buffer layer C, a middle layer (it may be called just “a bufferlayer” hereinafter) having almost the same compositions as those of thebuffer layer C (e.g., AlN and AlGaN) may be further formed in thesemiconductor substrate (semiconductor crystal A) periodically,alternatively with other layers, or deposited so that the middle layerhas a multiple layer structure.

By depositing such a buffer layer (or a middle layer), stress caused bydifference of lattice constants and acting to the semiconductor crystalA may be relaxed by the same action principle as that of theconventional one. As a result, crystallinity of the device is improved.

Such action and effect may be seen remarkable especially when themonocrystalline material B constructing the reaction prevention layer issuch as silicon carbide (SiC). In short, it is more preferable at thistime to form the buffer layer C on the reaction prevention layer.

The nineteenth aspect is drawn to a method according to the eighteenthaspect, wherein the buffer layer C is formed to have thickness of 0.01μm to 1 μm. More preferably, thickness of the buffer layer C is in arange of 0.02 μm to 0.5 μm.

When thickness of the buffer layer C is too large, cracks tend to begenerated in the buffer layer C and more production time and materialsare needed. That is not favorable to the production cost of the device.When the buffer layer C is too thin, it becomes difficult to form thebuffer layer to have almost uniform thickness. As a result, the bufferlayer becomes to have ununiform thickness (or a portion where it is notgrown properly), crystallinity of the buffer layer tends to beununiform, and that is not desirable.

The twentieth aspect is drawn to a method according to any one of thethirteenth to nineteenth aspects, further comprising a separationprocess for separating the semiconductor crystal A and the basesubstrate, wherein stress owing to differences of thermal expansioncoefficients is generated by cooling or heating the substrate crystal Aand the base substrate, and sidewalls of the cavities are broken byusing the stress.

For example, when the semiconductor substrate (semiconductor crystal A)is formed to have a sufficient thickness, inner stress or outer stressbecomes easy to act intensively to the sidewalls of the cavities. As aresult, especially these stress function as shearing stress toward thesidewalls of cavities. When the shearing stress becomes larger, the thinfilm part ruptures.

Accordingly, the base substrate and the semiconductor substrate can beeasily separated by applying the stress. The larger the cavity is, themore easily stress (shearing stress) concentrates to sidewalls of thecavity.

In short, according to the twentieth aspect described above, thesemiconductor crystal A and the base substrate can be easily separatedbecause it becomes easy to generate stress.

When the base substrate and the semiconductor substrate are separated(exfoliated), a part of the base substrate (e.g., rupture remains of thethin film part or sidewalls of the cavity) may remain on thesemiconductor substrate side. That is, this separation process does notnecessarily require complete or perfect separation of each material withno remains.

Such rupture remains may be removed by using conventional methods suchas wrapping and etching if necessary.

The twenty-first aspect is drawn to the crystal growing processaccording to any one of the thirteenth to twentieth aspects, wherein thesemiconductor crystal A is deposited to have a thickness of 50 μm ormore.

The larger thickness of the semiconductor crystal A is, the more tensilestress to the semiconductor substrate (semiconductor crystal A) isrelaxed. That decreases generation of dislocations and cracks in thesemiconductor substrate and at the same time strengthen thesemiconductor substrate. As a result, it becomes easier to concentratethe stress to sidewalls of the cavity.

Preferably, thickness of the thin film part is 20 μm or less. Thesmaller this thickness is, the more the tensile stress to thesemiconductor substrate (semiconductor crystal A) is relaxed. Thatresults in decreasing generation of dislocations and cracks in thesemiconductor substrate. But when thickness of the thin film part isless than 0.02 μm, a problem takes place in absolute strength of thethin film part itself, and high productivity of the device cannot bemaintained. So in order to keep the quality and the productivity of thecrystal growth substrate, the thin film part may preferably havethickness in a range of 0.02 μm to 20 μm.

Relatively, it is preferable that thickness of an objectivesemiconductor crystal which is formed by crystal growth is approximatelythe same or larger than that of the thin film part. By employing suchcondition, it becomes easier to relax stress toward the objectivesemiconductor crystal, to thereby control generation of dislocations andcracks in the semiconductor crystal more remarkably compared with aconventional invention. This stress relaxing effect grows largeraccording to that thickness of the objective semiconductor crystalgrowth relatively thicker. Although it depends on conditions such asthickness of the thin film part, this stress relaxing effect is almostsaturated with about 50 μm to 200 μm of the objective grownsemiconductor crystal when thickness of the thin film part is 20 μm orless.

The twenty-second aspect is drawn to a thin film part forming processaccording to any one of the thirteenth to twenty-first aspects, furthercomprising a concave part forming process in which a cavity whose top isopened is formed in silicon crystal comprising the base substratethrough physical or chemical etching treatment is carried out and then acavity and the thin-film part are formed by migration function aroundthe surface of the substrate owing to heat treatment at a temperature of1000° C. to 1350° C.

The twenty-third aspect is drawn to a thin film part forming processaccording to any one of the thirteenth to twenty-first aspects, the thinfilm part forming process comprising: an ion injecting process in whichion is injected into the silicon crystal forming the thin film part; aconcave part forming process in which a cavity whose top is opened isformed in the silicon crystal comprising the base substrate except forthe thin film part through physical or chemical etching treatment; ajunction process in which the thin film part is joined to the cavitypart through heat treatment; and an exfoliating process in which thethin film part is exfoliated at an ion injection part functioning as aseparation front.

At least the thin film part forming process in the present invention canbe or is easily carried out adequately and concretely according to thetwenty-second and twenty-third aspects. Here the thin film part formingprocess in the present invention is not necessarily limited thereto, butit may be carried out by employing appropriate method. That is, actionsand effects of the present invention may be obtained properly or morethan that by employing such method.

The twenty-fourth aspect is drawn to a thin film part forming processaccording to any one of the thirteenth to twenty-third aspects, whereinheight of the cavity is 0.1 μm to 10 μm. More preferably, height of thecavity may be 0.5 μm to 5 μm.

When height of the cavity is too large, strength of each pillar whichsupports a hole, a groove or a cavity becomes unstable or processing thepillars gradually becomes difficult and inefficient. That is notdesirable. Also that makes processing time of the device longer, tothereby delay its productivity.

When height of the cavity is too small, thin film part tends to joinwith the bottom surface of the cavity, and cavities cannot be obtainedsecurely. That is not desirable.

The twenty-fifth aspect is drawn to a group III nitride compoundsemiconductor device comprising the semiconductor crystal which isformed by the method of any one of the thirteenth to twenty-fourthaspects as a crystal growth substrate.

Accordingly, a group III nitride compound semiconductor device made of asemiconductor which has excellent crystallinity and less inner stresscan be obtained or easily produced.

The twenty-sixth aspect is to form a group III nitride compoundsemiconductor device by employing crystal growth in which asemiconductor crystal manufactured by the method of any one of thethirteenth to twenty-fourth aspects functions as a crystal growthsubstrate.

As a result, a group III nitride compound semiconductor device made of asemiconductor which has excellent crystallinity and less inner stresscan be obtained or easily produced.

Through employment of the aforementioned aspects of the presentinvention, the aforementioned drawbacks can be overcome effectively andrationally.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic sectional view showing a method for producing asemiconductor crystal according to the first feature of the presentinvention.

FIG. 2 is a schematic sectional view showing a method for producing asemiconductor crystal according to the second feature of the presentinvention.

FIG. 3 is a graph showing the relationship between number(concentration) of injected ion and depth of the injected ion accordingto the present invention.

FIG. 4 is a graph showing the relationship between depth (depth h at themaximum ion concentration) of ion injection and injection energy of ion.

FIG. 5 is a schematic cross-sectional view showing a conventionalsemiconductor crystal formed on Si substrate (base substrate).

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiments of the present invention will next be described withreference to the drawings. Characteristic features of the presentinvention which have been described above is also the best mode forcarrying out the invention, and the present invention is not limited tothe below-described specific embodiments.

On carrying out the present invention, each producing condition may bechosen from the followings. Also each producing condition may becombined arbitrary with each other.

Firstly, Group III nitride compound semiconductor layers are preferablyformed through metal-organic vapor phase growth (MOCVD or MOVPE). Othergrowth methods, such as molecular-beam epitaxy (MBE), halide vapor phasegrowth (halide VPE), and liquid phase growth (LPE), may also beemployed. Moreover, the respective layers may be formed throughdifferent methods.

Preferably, a buffer layer is appropriately provided in the crystalgrowth substrate or formed on such as the base substrate, for severalreasons, such as compensation of lattice mismatch.

Particularly, when the buffer layer (intermediate layer) is provided inthe semiconductor substrate (the substrate crystal A), the buffer layeris preferably formed from a Group III nitride compound semiconductorAl_(x)Ga_(y)In_(1-x-y)N (0≦x≦1; 0≦y≦1; 0≦x+y≦1) which is formed at lowtemperature, more preferably Al_(x)Ga_(1-x)N (0≦x≦1). The buffer layermay be a single layer or a multi-layer comprising a plurality of sublayers of different compositions. The buffer layer may be formed at alow temperature (380–420° C.), or may be formed at 1000–1180° C. throughMOCVD. Alternatively, a buffer layer comprising AlN may be formedthrough reactive sputtering by use of a DC magnetron sputteringapparatus, from high-purity metallic aluminum and nitrogen gas servingas raw materials.

The buffer layer comprising a compound semiconductor represented byformula Al_(x)Ga_(y)In_(1-x-y)N (0≦x≦1; 0≦y≦1; 0≦x+y≦1; arbitrarycompositional proportions) can be formed through physical vapordeposition such as vapor deposition, ion plating, laser ablation, orECR. The buffer layer is preferably formed through physical vapordeposition at 200–600° C., more preferably 300–600° C., most preferably350–450° C. The buffer layer which is formed through physical vapordeposition such as sputtering preferably has a thickness of 100–3,000 Å,more preferably 100–400 Å, most preferably 100–300 Å.

A buffer layer of multi-layer type is formed through any of severalmethods. For example, an Al_(x)Ga_(1-x)N (0≦x≦1) layer and a GaN layerare alternately formed, or a semiconductor layer of the same compositionis alternately formed at different temperatures, such as 600° C. orlower and 1000° C. or higher. These two methods may be employed incombination. The multi-layer buffer layer may be formed by stacking atleast three species selected from Group III nitride compoundsemiconductors represented by Al_(x)Ga_(y)In_(1-x-y)N (0≦x≦1; 0≦y≦1;0≦x+y≦1). Generally, a buffer layer is made of non-crystal and anintermediate layer is made of monocrystalline. Repetitions of unit of abuffer layer and an intermediate layer may be formed, and the number ofrepetitions is not particularly limited. The larger the number ofrepetitions are, the greater the improvement in crystallinity becomes.

The present invention is substantially applicable even when thecomposition of a buffer layer and that of a Group III nitride compoundsemiconductor formed on the buffer layer are such that a portion ofGroup III elements are replaced with boron (B) or thallium (Tl) or aportion of nitrogen (N) atoms are replaced with phosphorus (P), arsenic(As), antimony (Sb), or bismuth (Bi). Also, the buffer layer and theGroup III nitride compound semiconductor may be doped with any one ofthese elements to such an extent as not to appear in the compositionthereof. For example, a Group III nitride compound semiconductor whichis represented by Al_(x)Ga_(1-x)N (0≦x≦1) and which does not containindium (In) and arsenic (As) may be doped with indium (In), which islarger in atomic radius than aluminum (Al) and gallium (Ga), or arsenic(As), which is larger in atomic radius than nitrogen (N), to therebyimprove crystallinity through compensation, by means of compressionstrain, for crystalline expansion strain induced by dropping off ofnitrogen atoms.

In this case, since acceptor impurities easily occupy the sites of GroupIII atoms, p-type crystals can be obtained as grown. Through thethus-attained improvement of crystallinity combined with the features ofthe present invention, threading dislocation can be further reduced toapproximately 1/100 to 1/1000. In the case of an underlying layercontaining two or more repetitions of a buffer layer and a Group IIInitride compound semiconductor layer, the Group III nitride compoundsemiconductor layers are further preferably doped with an elementgreater in atomic radius than a predominant component element. When alight-emitting element is produced, use of a binary or ternary Group IIInitride compound semiconductor is preferred.

When an n-type Group III nitride compound semiconductor layer is to beformed, a Group IV or Group VI element, such as Si, Ge, Se, Te, or C,can be added as an n-type impurity. A Group II or Group IV element, suchas Zn, Mg, Be, Ca, Sr, or Ba, can be added as a p-type impurity. Thesame layer may be doped with a plurality of n-type or p-type impuritiesor doped with both n-type and p-type impurities.

Dislocations occurring in a Group III nitride compound semiconductorlayer can also be reduced through employment of lateral epitaxialgrowth. In this case, lateral epitaxial growth can be performed in anarbitrary manner; e.g., by use of a mask or through employment ofetching for leveling a step and supplying the step as seed for executingELO between steps.

The aforementioned etching mask may be formed from a polycrystallinesemiconductor such as polycrystalline silicon or polycrystalline nitridesemiconductor; an oxide or nitride such as silicon oxide (SiO_(x)),silicon nitride (SiN_(x)), titanium oxide (TiO_(x)), or zirconium oxide(ZrO_(x)); or a high-melting-point metal such as titanium (Ti) ortungsten (W). A multi-layer film of these materials may also beemployed. The film can be formed through any film formation method suchas vapor phase growth (e.g., vapor deposition, sputtering, or CVD).

Although reactive ion beam etching (RIBE) is a preferred etching method,any other etching method can also be employed. A step having a surfaceof a side wall which is not normal to the substrate plane may be formed.For example, a step which does not have a flat surface on the bottom ofthe substrate and which has a V-shape cross-section may be formedthrough anisotropic etching.

A semiconductor device, such as an FET or a light-emitting device, canbe formed on the aforementioned Group III nitride compoundsemiconductor. In the case where a light-emitting device is formed, alight-emitting layer may have a multi-quantum well (MQW) structure, or asingle-quantum well (SQW) structure, and the device may have ahomo-structure, a single-hetero-structure, or a double-hetero-structure,or the layer may be formed by means of, for example, a pin junction or apn junction.

Embodiments of the present invention will next be described. The presentinvention is not limited to the embodiments described below.

(First Embodiment)

In the following Example, a method for producing a semiconductor crystal(crystal growth substrate) according to a first embodiment of thepresent invention will be described.

[1] Buffer Layer Forming Process

First, about 0.2 μm to 0.3 μm in thickness of Al_(x)Ga_(1-x)N (x≈0.20)buffer layer C is formed at a temperature of about 1100° C. throughmetal organic vapor phase epitaxy (MOVPE) on a Si (111) substrate.

[2] Sacrifice Layer Growing Process

Next, about 1 μm in thickness of GaN is formed as a sacrifice layer at atemperature of about 1100° C. through vapor phase growth (MOVPE).

[3] Reaction Prevention Layer Forming Process

In this reaction prevention layer forming process, a reaction preventionlayer is deposited on the above described sacrifice layer.

In this process, about 1 μm in thickness of aluminum nitride (AlN)reaction prevention layer B is formed on the sacrifice layer at atemperature of about 1100° C. through vapor phase growth (MOVPE).

[4] Crystal Growing Process

In the crystal growing process, a semiconductor crystal A (GaN) is grownon the reaction prevention layer B to have thickness of about 200 μmthrough halide vapor phase growth (HVPE).

That is, about 200 μm in thickness of GaN layer (semiconductor crystalA) is grown on the reaction prevention layer B through halide vaporphase growth (HVPE). Crystal growth velocity of the GaN layer 102 bthough HVPE was about 45 μm/Hr.

[5] Separating Process

(a) After the crystal growing process, the wafer comprising the basesubstrate (Si substrate) was cooled to ambient temperature underconditions of supplying ammonia (NH₃) gas to a reaction chamber of thecrystal growth apparatus. Here velocity of cooling the layers was about−50° C./min to −5° C./min.

(b) The wafer comprising the base substrate (Si substrate) was takenfrom the reaction chamber of the crystal growth apparatus, and then GaNcrystal (semiconductor crystal A) exfoliated (or peeled off) from thebase substrate (Si substrate) was obtained. Here the crystal obtainedthrough this process was the GaN layer (semiconductor substrate) onwhose back surface remains of the sacrifice layer and the reactionprevention layer each comprising a reaction part were left.

[6] Remains Removing Process

After carrying out the above separating process, rupture remains of thesacrifice layer and the reaction prevention layer each of whichcomprised a reaction part and was remaining on the back surface of theGaN crystal were removed through wrapping process.

Here this removing process may be carried out through etching treatmentusing a mixture of hydrofluoric acid and nitric acid. When the reactionprevention layer B has enough conductivity, the reaction preventionlayer B may not be removed. For example, whether to carry out theremains removing process or not can be selected according to conditionssuch as the structure of electrode connection of the light-emittingsemiconductor device.

Accordingly, a GaN crystal (GaN layer 102 b) having thickness of about200 μm and excellent crystallinity, which is a desired free-standingsemiconductor substrate independent from the base substrate 101, wasobtained through the method described above.

By employing this method for producing a semiconductor crystal, a singlecrystalline gallium nitride (GaN) which has more excellent crystallinitythan that of a conventional one and has no GaN polycrystalline (reactionpart) or no crack can be obtained.

Accordingly, by employing such an excellent single crystalline to aportion of a semiconductor light-emitting device, e.g., to a crystalgrowth substrate, it becomes possible or easier to produce asemiconductor product, e.g., a semiconductor light-emitting device and asemiconductor light-receiving device, which has a high luminousefficiency and whose driving voltage is more decreased compared with aconventional device.

Also, by employing such an excellent single crystalline, it becomespossible or easier to produce not only a luminous device but alsosemiconductor electron device such as a semiconductor power devicehaving a high voltage-withstand-characteristic and a semiconductorhigh-frequency device which works to a high frequency.

Alternatively, in order to correct lattice constant mismatch, a bufferlayer forming process in which crystal growth is carried out at a hightemperature of 1000° C. to 1180° C. may be further employed between thereaction prevention layer forming process and the crystal growthprocess.

Alternatively, materials such as Al_(x)Ga_(1-x)N (0<x<1) may be used asmonocrystalline material B for forming the reaction prevention layer.Approximately same action and effect as in this embodiment may beobtained by employing such monocrystalline material B.

More generally, silicon carbide (SiC), aluminum nitride (AlN), spinel(MgAl₂O₄), or AlGaN, AlInN and AlGaInN whose aluminum composition ratiois at least 0.30 and more may be used as monocrystalline material B forforming the reaction prevention layer.

The semiconductor crystal A which forms an objective semiconductorsubstrate is not limited to gallium nitride (GaN) but may be selectedfrom the above-mentioned group III nitride compound semiconductor.

Alternatively, the objective semiconductor substrate (semiconductorcrystal A) may have a multiple layer structure.

For example, growth temperature of the semiconductor crystal Aconstituting the objective semiconductor substrate may be raised inhalfway of its growing process and a semiconductor layer grown at highertemperature may be formed at the upper portion (upper layer). As aresult, the same action and effect as in the present invention may beobtained by forming the semiconductor layer having multiple layerstructure or by forming a middle layer such as a buffer layer in themultiple layer structure.

Further, materials of “a sacrifice layer” may not be necessarily thesame as those of the objective semiconductor substrate (semiconductorcrystal A). The materials of “a sacrifice layer” may also be arbitraryselected among the above-mentioned general “Group III nitride compoundsemiconductor.”

In short, kinds (materials) of the sacrifice layer and the objectivesemiconductor crystal are not particularly limited in the presentinvention, and the present invention can be applied to well-known orarbitrary kind of hetero-epitaxial growth on the base substrate (Sisubstrate) described above.

In the above embodiment, metal-organic vapor phase epitaxly (MOVPE) isemployed in the above embodiment. Alternatively, crystal growth of thepresent invention may be carried out through halide vapor phase growth(HVPE).

Further, in the above embodiment, the semiconductor crystal A isemployed as a crystal growth substrate of the semiconductor device afterseparating the base substrate and removing the remains. Alternatively,processes of separating the base substrate and removing the remains maybe carried out after depositing the semiconductor layer of thesemiconductor device. Further alternatively, the semiconductor crystal Amay be used as a semiconductor device without particularly carrying outthe separating process and the remains removing process.

(Second Embodiment)

In the following Example, a method for producing a semiconductor crystal(crystal growth substrate) according to a second embodiment of thepresent invention will be described.

[1] Thin-Film Part Forming Process

In this process, a concave part forming process in which a cavity whosetop is opened is formed in silicon crystal as a base substrate throughphysical or chemical etching treatment is carried out and then a cavityand a thin-film part are formed by migration function around the surfaceof the substrate owing to heat treatment at a temperature of 1000° C. to1200° C.

(a) Forming a Concave Part on a Silicon Substrate

About 1 μm in thickness of SiO₂ film is formed on a Si (111) substrateby using plasma chemical vapor deposition (CVD) device, a portion of theSiO₂ film and the Si substrate are patterned or etched by employingphotolithography and RIE, and many holes each having about 0.8 μm indiameter and about 3 μm in depth are formed on the surface of the Si(111) substrate at a period (interval) of 1.2 μm.

Then the SiO₂ film is removed through B—HF.

(b) Migration

Next, the Si substrate in which the concave parts are formed is treatedby a heat treatment at a temperature of 1100° C. in the atmosphere of H₂gas to migrate Si atoms at the surface of the substrate, to therebyobtain about 1 μm in thickness of thin-film part (membrane) on the upperportion of each concave part. In short, by forming the thin-film part D1to close the upper portion of the concave part, a lot of cavities asshown in FIG. 2 are obtained. After that, the substrate is wet-oxidizedat a temperature of 1150° C., its surface is changed into SiO₂ and therest of the Si thin-film part becomes to have a thickness of about 0.1μm.

(c) Washing

Then, the SiO₂ film is removed by employing buffered hydrofluoric acid.

By carrying out the above processes (a) to (c), a Si substrate Dcomprising cavities as shown in FIG. 2 and the thin-film part D1 isobtained.

[2] Reaction Prevention Layer Forming Process

A reaction prevention layer forming process is a process for depositinga reaction prevention layer on a base substrate (Si substrate D) whichcomprises the thin-film part D1.

In this process, first, about 1 μm in thickness of a reaction preventionlayer B made of aluminum nitride (AlN) is formed at a temperature ofabout 1100° C. on the crystal growth plane (thin-film part D1) of the Si(111) substrate through metal organic chemical vapor deposition (MOCVD).

[3] Crystal Growing Process

In the crystal growing process, a semiconductor crystal A (GaN) is grownon the surface of the reaction prevention layer B to have a thickness ofabout 200 μm through metal-organic vapor phase epitaxy (hereinaftercalled “MOVPE”).

In this process, the following gasses were employed: ammonia (NH₃),carrier gas (H₂ or N₂), trimethylgallium (Ga(CH₃)₃, hereinafter called“TMG”), and trimethylaluminum (Al(CH₃)₃, hereinafter called “TMA”).

A GaN layer (semiconductor crystal A) is grown on the reactionprevention layer B by crystal growth through MOVPE treatment until itsthickness becomes 200 μm. Crystal growth velocity of the GaN layerthough MOVPE is about 301 m/Hr.

[4] Separating Process

(a) After the crystal growing process, a wafer comprising the basesubstrate (Si substrate) is cooled to ambient temperature underconditions of supplying ammonia (NH₃) gas to a reaction chamber of thecrystal growth apparatus. Here velocity of cooling the layers may beabout −50° C./min to −5° C./min.

(b) The wafer comprising the base substrate (Si substrate) is taken fromthe reaction chamber of the crystal growth apparatus, and then GaNcrystal (semiconductor crystal A) exfoliated (or peeled off) from thebase substrate (Si substrate) is obtained. Here the crystal obtainedthrough this process is the GaN layer (semiconductor substrate) on whoseback surface rupture remains of the thin-film part D1 and sidewall ofthe cavities are left.

[5] Remains Removing Process

After carrying out the above separating process, rupture remains of thethin-film part D1 made of Si and sidewall of the cavities which remainon the back surface of the GaN crystal is removed through wrappingprocess.

Here this removing process may be carried out through etching treatmentusing a mixture of hydrofluoric acid and nitric acid. And the reactionprevention layer B may be also removed.

Accordingly, a GaN crystal (GaN layer) having a thickness of about 200μm and excellent crystallinity, which is an objective free-standingsemiconductor substrate (semiconductor crystal A) independent from thebase substrate, was obtained through the method described above.

By employing this method for producing a semiconductor crystal, a singlecrystalline gallium nitride (GaN) which has more excellent crystallinitythan that of a conventional one and has no GaN polycrystalline (reactionpart) or no crack can be obtained.

Accordingly, by employing such an excellent single crystalline to aportion of a semiconductor light-emitting device, e.g., to a crystalgrowth substrate, it becomes possible or easier to produce asemiconductor product, e.g., a semiconductor light-emitting device and asemiconductor light-receiving device, which has a high luminousefficiency and whose driving voltage is more decreased compared with aconventional device.

Also, by employing such an excellent single crystalline, it becomespossible or easier to produce not only a luminous device but alsosemiconductor electron device such as a semiconductor power devicehaving a high voltage-withstand-characteristic and a semiconductorhigh-frequency device which works to a high frequency.

Alternatively, in order to correct the mismatch of lattice constant, abuffer layer forming process in which crystal growth is carried out at ahigh temperature of 1000° C. to 1180° C. may be further employed betweenthe reaction prevention layer forming process and the crystal growthprocess.

In the above embodiment, the thin-film part of the base substrate isobtained by forming a lot of cavities near the crystal growth plane ofthe base substrate as shown in FIG. 2. Alternatively, the cavities maybe formed in sequence. Accordingly, in the present invention, the cavitymay be formed, for example, such that one long and narrow tubular tunnelis formed elaborately in a scroll shape. FIG. 2 of this case can beinterpreted as a sectional view of the base substrate comprising such acavity.

In short, the conditions of a cavity which is objected to form the thinfilm part of the base substrate, such as shape, size, interval,arrangement and orientation, are generally arbitral.

(Third Embodiment)

In the present embodiment, the thin film part forming process in thesecond embodiment is replaced with “thin film part forming process”described below. With respect to other processes, the same processes asin the second embodiment may be carried out.

So, in this embodiment, the “thin film part forming process” which makesthe third embodiment different from the second embodiment may beexplained.

[1] Thin Film Part Forming Process

This process is for forming a cavity and a thin film part, comprising anion injection process in which ion is injected into a silicon crystalproviding a thin film part, a concave part forming process in which acavity whose top is opened is formed in the silicon crystal constitutingthe base substrate except for the thin film part through physical orchemical etching treatment, a junction process in which the thin filmpart is joined to the cavity part through heat treatment, and anexfoliating process in which the thin film part is exfoliated at an ioninjection part functioning as a separation front.

(a) Ion Injection Process

Hydrogen ion is injected into the silicon crystal (Si (111) substrate)which provides the thin film part D1 at a doping rate of 2×10¹⁶ to1×10¹⁷ [cm⁻²] and an injection energy of 4 keV.

FIG. 3 is a graph showing the relationship between the number(concentration) of injected ion and depth of injecting ion in thisembodiment. By injecting ion, as shown in FIG. 3, an ion injection layerwhose ion concentration is locally high is formed around the surface ofthe ion injection plane of the silicon crystal.

(b) Cavity Part Forming Process

On the contrary, about 1 μm in thickness of a SiO₂ film is formed onanother Si (111) substrate (represented by D in FIG. 2) by using plasmachemical vapor deposition (CVD) device, a portion of the SiO₂ film andthe Si substrate are patterned or etched by employing photolithographyand RIE, and many pillars each having about 0.6 μm in diameter and about3 μm in depth are formed on the surface of the Si (111) substrate at aperiod (interval) of 2 μm.

(c) Junction Process

Next, the ion injection front of the silicon crystal which provides thethin film part D1 is joined vertically to the pillars formed on thesurface of the Si substrate.

(d) Exfoliating Process

The silicon crystal which provides the thin film part D1 is separated atthe ion injection part through heat treatment at a temperature of 500°C. and a cavity whose top is closed by the thin film part D1 isobtained.

By carrying out the above processes (a) to (d), an Si substrate Dcomprising cavities and the thin film part D as shown in FIG. 2 isobtained.

Then ranges for a modified embodiment of the third embodiment areexplained hereinafter.

For example, helium ion (He⁺) in place of hydrogen ion (H⁺) may be usedto obtain action and effect of the above embodiment.

Doping amount of hydrogen ion may be, although it depends on a materialused to form the base layer, about 1×10¹⁵ [cm²] to 1×10²⁰ [cm²] toobtain approximately the same action and effect as those of the aboveembodiment. More preferably, doping amount of hydrogen ion may be about3×10¹⁵[/cm²] to 1×10¹⁷[/cm²], and further preferably, it may be about8×10¹⁵[/cm²] to 2×10¹⁶[/cm²].

When doping amount of hydrogen ion is too small, it becomes difficult tosecurely separate the thin film part D1 from the silicon crystal whichprovides the thin film part D1. When doping amount of hydrogen ion istoo big, the thin film part D1 may be largely damaged and it becomesdifficult to separate the thin film part D1 which has a form of onesheet with substantially uniform thickness from the base substrate.

Alternatively, the thickness of the thin film part separated from thebase substrate can be controlled by varying the incident energy. FIG. 4illustrates the result of measuring depth (depth h at the maximum ionconcentration) of injecting ion toward injection energy of ion.Accordingly, for example, because the depth of ion injection (depth h atthe maximum ion concentration) is approximately in proportion toinjection energy of ion, the thickness of the thin film part may becontrolled properly by adjusting the amount of incident energy(accelerating voltage).

By carrying out heat treatment after ion injection process, a partialruptured part (void) is formed at the ion injection layer in advance andcrystallinity of the ion injection part of the base substrate, which isdamaged by ion irradiation, can be recovered.

By carrying out heat treatment to the thin film part D1 in the cavityforming process, crystallinity of the semiconductor formed thereon canbe improved.

Thickness of the thin film part D1 may preferably 20 μm or less. Thethinner then thin film part is, the more tensile stress toward theobjective grown semiconductor crystal is relaxed, and that can decreasegeneration of dislocations or cracks in the objective grownsemiconductor crystal. More preferably, thickness of the thin film partmay be 2 μm or less, and further preferably, 200 nm or less. In order toobtain the thin film part having such an optimum thickness, ioninjection energy (accelerating voltage) may be controlled in accordancewith the graph in FIG. 4 so that the depth when the numbers of injectedion becomes its peak corresponds to the desired thickness of the thinfilm part.

When the ion injection layer becomes too thick, it becomes difficult tocontrol thickness of the thin film part. So thickness of the ioninjection layer has to be determined carefully.

Although thickness of the ion injection layer cannot be strictlydefined, the full width half maximum in the characteristics of thenumbers of injected ion in FIG. 3, for example, may be used as onestandard. The thinner the ion injection layer is, the easier thethickness of the thin film part of the base substrate becomes to becontrolled.

Accordingly, in order to control thickness of the thin film partprecisely, a method for keeping the energy of ion injection(accelerating voltage) constant as much as possible may be useful.

Alternatively, in the second embodiment and each embodiment followingthe second embodiment, materials such as Al_(x)Ga_(1-x)N (0<x<1) may beused as monocrystalline material B for forming the reaction preventionlayer to obtain approximately same action and effect as in the aboveembodiments. More generally, silicon carbide (SiC), aluminum nitride(AlN), spinel (MgAl₂O₄), or AlGaN, AlInN and AlGaInN whose aluminumcomposition ratio is at least 0.30 and more may be used asmonocrystalline material B forming the reaction prevention layer.

The semiconductor crystal A which forms an objective semiconductorsubstrate is not limited to gallium nitride (GaN) but may be selectedfrom the above-mentioned group III nitride compound semiconductor.

Alternatively, the objective semiconductor substrate (semiconductorcrystal A) may have a multiple layer structure.

In short, in the present invention, kinds (materials) of the basesubstrate and the objective semiconductor crystal have no speciallimitation. So the present invention, including the above-describedarbitrary combination of each material of the base substrate and thesemiconductor crystal, can be applied to well-known and arbitral kind ofhetero epitaxial growth.

Metal-organic vapor phase epitaxly (MOVPE) is employed in the aboveembodiment. Alternatively, crystal growth of the present invention maybe carried out through halide vapor phase growth (HVPE).

Further, in the above embodiment, the semiconductor crystal A isemployed as a crystal growth substrate of the semiconductor device afterseparating the base substrate and removing the remains. Alternatively,processes of separating the base substrate and removing the remains maybe carried out after depositing the semiconductor layer of thesemiconductor device. Further alternatively, the semiconductor crystal Amay be used as a semiconductor device without particularly carrying outthe separating process and the remains removing process.

While the present invention has been described with reference to theabove embodiments as the most practical and optimum ones, the presentinvention is not limited thereto, but may be modified as appropriatewithout departing from the spirit of the invention.

1. A method for producing a semiconductor substrate in which asemiconductor crystal A comprising a Group III nitride compoundsemiconductor is grown on a base substrate comprising silicon (Si), saidmethod comprising: a sacrifice layer forming process in which asacrifice layer made of approximately the same kind of semiconductor assaid semiconductor crystal A is formed on said base substrate by crystalgrowth; a reaction prevention layer forming process in which a reactionprevention layer made of a monocrystalline material B whose meltingpoint or thermal stability is higher than that of said semiconductorcrystal A and preventing silicon (Si) from diffusing is deposited onsaid sacrifice layer; and a crystal growth process for growing asemiconductor substrate made of said semiconductor crystal A on saidreaction prevention layer by crystal growth.
 2. A method for producing asemiconductor substrate according to claim 1, wherein said semiconductorcrystal A comprises a group III nitride compound semiconductor having acomposition of Al_(x)Ga_(y)In(_(1-x-y))N (0≦x<0.9, 0.1<y≦1, 0<x+y≦1). 3.A method for producing a semiconductor substrate according to claim 1,wherein at least one of silicon carbide (SiC), aluminum nitride (AlN),and spinel (MgAl₂O₄) is used as monocrystalline material B forming saidreaction prevention layer.
 4. A method for producing a semiconductorsubstrate according to claim 2, wherein at least one of silicon carbide(SiC), aluminum nitride (AlN), and spinel (MgAl₂O₄) is used asmonocrystalline material B forming said reaction prevention layer.
 5. Amethod for producing a semiconductor substrate according to claim 1,wherein AlGaN, AlInN, or AlGaInN, in which an aluminum composition ratiois at least 0.30 or more, is used as monocrystalline material B formingsaid reaction prevention layer.
 6. A method for producing asemiconductor substrate according to claim 2, wherein AlGaN, AlInN, orAlGaInN, in which an aluminum composition ratio is at least 0.30 ormore, is used as monocrystalline material B forming said reactionprevention layer.
 7. A method for producing a semiconductor substrateaccording to claim 1, wherein a thickness of said reaction preventionlayer is in a range of 0.1 mm to 2 mm.
 8. A method for producing asemiconductor substrate according to claim 2, wherein a thickness ofsaid reaction prevention layer is in a range of 0.1 mm to 2 mm.
 9. Amethod for producing a semiconductor substrate according to claim 1,wherein two or more reaction prevention layers are deposited.
 10. Amethod for producing a semiconductor substrate according to claim 2,wherein two or more reaction prevention layers are deposited.
 11. Amethod for producing a semiconductor substrate according to claim 1,wherein a buffer layer C made of Al_(x)Ga_(1-x)N (0<x≦1) is formeddirectly on said base substrate or said reaction prevention layer.
 12. Amethod for producing a semiconductor substrate according to claim 11,wherein a buffer layer C made of Al_(x)Ga_(1-x)N (0<x≦1) is formeddirectly on said base substrate or said reaction prevention layer.
 13. Amethod for producing a semiconductor substrate according to claim 11,wherein two or more buffer layers C are formed.
 14. A method forproducing a semiconductor substrate according to claim 12, wherein twoor more buffer layers C are formed.
 15. A method for producing asemiconductor substrate according to claim 11, wherein said buffer layerC is formed to have a thickness of 0.01 mm to 1 mm.
 16. A method forproducing a semiconductor substrate according to claim 1, wherein saidbuffer layer C is formed to have a thickness of 0.01 mm to 1 mm.
 17. Amethod for producing a semiconductor substrate according to claim 1,wherein said semiconductor crystal A is deposited to have a thickness of50 mm or more in said crystal growing process.
 18. A method forproducing a semiconductor substrate according to claim 2, wherein saidsemiconductor crystal A is deposited to have a thickness of 50 mm ormore in said crystal growing process.
 19. A method for producing asemiconductor substrate in which a semiconductor crystal A comprising aGroup III nitride compound semiconductor is grown on a base substratecomprising silicon (Si), said method comprising: a thin film partforming process in which a thin film part made of silicon (Si) is formedas a crystal growth front of said base substrate by forming a cavityright under said crystal growth front of said base substrate; a reactionprevention layer forming process in which a reaction prevention layermade of a monocrystalline material B whose melting point or thermalstability is higher than that of said semiconductor crystal A isdeposited on said thin film part; and a crystal growing process forgrowing said semiconductor crystal A on said reaction prevention layerby crystal growth. wherein said cavity is separated into a plurality ofcavities which are independent with each other on an upper side of saidbase substrate.
 20. A method for producing a semiconductor substrateaccording to claim 19, wherein said semiconductor crystal A comprises agroup III nitride compound semiconductor having a composition ofAl_(x)Ga_(y)In(_(1-x-y))N (0≦x<1, 0<y≦1, 0<x+y≦1).
 21. A method forproducing a semiconductor substrate according to claim 19, wherein atleast one of silicon carbide (SiC), aluminum nitride (AlN), and spinel(MgAl₂O4) is used as monocrystalline material B forming said reactionprevention layer.
 22. A method for producing a semiconductor substrateaccording to claim 20, wherein at least one of silicon carbide (SiC),aluminum nitride (AlN), and spinel (MgAl₂O₄) is used as monocrystallinematerial B forming said reaction prevention layer.
 23. A method forproducing a semiconductor substrate according to claim 19, whereinAlGaN, AlInN, or AlGaInIN, in which an aluminum composition ratio is atleast 0.30 or more, is used as monocrystalline material B forming saidreaction prevention layer.
 24. A method for producing a semiconductorsubstrate according to claim 20, wherein AlGaN, AllnIN, or AIGaInN, inwhich an aluminum composition ratio is at least 0.30 or more, is used asmonocrystalline material B forming said reaction prevention layer.
 25. Amethod for producing a semiconductor substrate according to claim 19,wherein a thickness of said reaction prevention layer is in a range of0.1 mm to 2 mm.
 26. A method for producing a semiconductor substrateaccording to claim 20, wherein a thickness of said reaction preventionlayer is in a range of 0.1 mm to 2 mm.
 27. A method for producing asemiconductor substrate according to claim 19, further comprising areaction prevention layer forming process wherein a buffer layer C madeof Al_(x)Ga_(1-x)N (0<x≦1) is formed on said reaction prevention layerafter said reaction prevention layer forming process.
 28. A method forproducing a semiconductor substrate according to claim 20, furthercomprising a reaction prevention layer forming process wherein a bufferlayer C made of Al_(x)Ga_(1-x)N (0<x≦1) is formed on said reactionprevention layer after said reaction prevention layer forming process.29. A method for producing a semiconductor substrate according to claim27, wherein said buffer layer C is formed to have a thickness of 0.01 mmto 1 mm.
 30. A method for producing a semiconductor substrate accordingto claim 28, wherein said buffer layer C is formed to have a thicknessof 0.01 mm to 1 mm.
 31. A method for producing a semiconductor substrateaccording to claim 19, further comprising a separation process forseparating said semiconductor crystal A and said base substrate, whereinstress owing to differences of thermal expansion coefficients isgenerated by cooling or heating said substrate crystal A and said basesubstrate, and sidewalls of said cavity is broken by using said stress.32. A method for producing a semiconductor substrate according to claim20, further comprising a separation process for separating saidsemiconductor crystal A and said base substrate, wherein stress owing todifferences of thermal expansion coefficients is generated by cooling orheating said substrate crystal A and said base substrate, and sidewallsof said cavity is broken by using said stress.
 33. A method forproducing a semiconductor substrate according to claim 19, wherein saidsemiconductor crystal A is deposited to have a thickness of 50 mm ormore in said crystal growing process.
 34. A method for producing asemiconductor substrate according to claim 20, wherein saidsemiconductor crystal A is deposited to have a thickness of 50 mm ormore in said crystal growing process.
 35. A method for producing asemiconductor substrate according to claim 19, said thin film partforming process comprising: a concave part forming process in which acavity whose top is opened is formed in said silicon crystalconstituting said base substrate through physical or chemical etchingtreatment is carried out; wherein a cavity and said thin film part areformed by migration function around said surface of said substrate owingto heat treatment at a temperature of 1000° C. to 1350° C.
 36. A methodfor producing a semiconductor substrate according to claim 20, said thinfilm part forming process comprising: a concave part forming process inwhich a cavity whose top is opened is formed in said silicon crystalconstituting said base substrate through physical or chemical etchingtreatment is carried out; wherein a cavity and said thin film part areformed by migration function around said surface of said substrate owingto heat treatment at a temperature of 1000° C. to 1350° C.
 37. A methodfor producing a semiconductor substrate according to claim 19, said thinfilm part forming process comprising: an ion injecting process in whichion is injected into said silicon crystal forming said thin film part; aconcave part forming process in which a cavity whose top is opened isformed in said silicon crystal comprising said base substrate except forsaid thin film part through physical or chemical etching treatment; ajunction process in which said thin film part is joined to said cavitypart through heat treatment; and an exfoliating process in which saidthin film part is exfoliated at an ion injection part functioning as aseparation front.
 38. A method for producing a semiconductor substrateaccording to claim 20, said thin film part forming process comprising:an ion injecting process in which ion is injected into said siliconcrystal forming said thin film part; a concave part forming process inwhich a cavity whose top is opened is formed in said silicon crystalcomprising said base substrate except for said thin film part throughphysical or chemical etching treatment; a junction process in which saidthin film part is joined to said cavity part through heat treatment; andan exfoliating process in which said thin film part is exfoliated at anion injection part functioning as a separation front.
 39. A method forproducing a semiconductor substrate according to claim 19, wherein aheight of said cavity is 0.1 mm to 10 mm in said thin film part formingprocess.
 40. A method for producing a semiconductor substrate accordingto claim 20, wherein a height of said cavity is 0.1 mm to 10 mm in saidthin film part forming process.